Explore Intel Fellow Mark Bohr's presentation from the Intel Developer Forum 2014, which covers some of the benefits of the new 14 nm transistor process, like improved area scaling, and microarchitecture optimizations for active power reduction.
White Paper: How to implement a 64B PCIe* burst transfer on Intel® architecture using cache attributes and fence instructions. (v.001, Feb. 2013)
White Paper: How to implement a 64B PCIe* burst transfer on Intel® architecture through the CPU core bus interface unit to a memory region reserved for a PCIe* device using cache attributes and fence instructions. (v.001, Feb. 2013)
White Paper: the Intel® QuickPath Interconnect links stitch together processors in distributed shared memory platform architecture.
The Intel® QuickPath Interconnect is a high-speed, packetized, point-to-point interconnect used in Intel’s next generation of microprocessors. The narrow high-speed links stitch together processors in a distributed shared memory platform architecture.
Introducing 3D transistors manufactured at 22 nm for future microprocessor families, continuing pursuit of Moore's Law.
Introducing a fundamentally different technology for future microprocessor families, 3D transistors manufactured at 22 nm, enabling Intel to continue to pursue Moore's Law.
Intel introduces innovative silicon technology processes, delivering leaps in performance and energy efficiency while enabling richer applications.
Following Moore's Law, Intel introduce new silicon technology processes, which deliver incredible leaps in performance and new levels of energy efficiency, performance, and richer end-user applications.
Backgrounder: Intel's 22 nm innovation ushers in new semiconductor technology and ensures the continuation of Moore's Law.
For the first time in history, silicon transistors are entering the third dimension. Intel is introducing the tri-gate transistor, in which the transistor channel is raised into the 3rd dimension.