Processing Multiple Buffers in Parallel for Performance
This paper describes how processing multiple independent data buffers in parallel can dramatically improve performance, even without SIMD. A scheduler allows this approach to be used even when the size of each individual buffer varies. The net result is a 2X - 3X improvement in performance over the best-known single-buffer methods on Intel® processors.
Connecting the internet of things through the use of common Intel® Architecture
Tieto, Intel team up to create flexible and scalable technologies used in 4G integration networks.
Demo on Intel® architecture shows performance benefits for app packet management at RSA 2014.
RSA 2014 demo shows how HyperScan* software helps efficiently match large data sets and patterns.
DPI on Wind River Open Virtualization* demo at RSA 2014 shows improved network security.
Intel’s Jim St. Leger and NEC’s Kuzuhiko Harasaki, discuss vEPC* solutions and Intel® DPDK for NFV.